“FPGA-InsideOut” is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA’s internal logic.

Session1 – сovering the following hardware design concepts (CRC – cyclic redundancy check, Parallel CRC, LFSR, sequential and combinational logic, reset, clock):

русская версия/russian version

If you want to replicate this exercise yourself on FPGA, you can find Verilog source code on: