documentation & videos

“ Ver1”:

The aim of “ Ver1” project is to build an FPGA-based universal line-rate ethernet over IP encapsulator – the network overlay appliance that can create L2 virtual ethernet links over L3 network (EoIP, EoMPLS, VxLAN, PBB etc).

“ Ver1” offers VLAN support where traffic for different vlans can be encapsulated with different L3 headers. L3 headers may not just be a static headers (like it was in “Ethernet Hardware Encapsulator” project) but they also may contain dynamically derived values. For example in order to encapsulate ethernet in IPv4, the IPv4 header’s “checksum” field must be dynamically calculated. This functionality implemented in “ Ver1” makes encapsulator “universal” – be capable of supporting every possible encapsulation protocol.

Please watch this video explaining operational principles of the system followed by the demonstration of the working hardware:

Documentation and source code for “ Ver1” project can be found at:


“EHA – Ethernet Hardware Encapsulator” – legacy project:

You might also be interested to see the predecessor of “ Ver1”  – a project named “EHA – Ethernet Hardware Encapsulator”.

This is a simple encapsulator device which receives frames on L2 ethernet interface, performs wire-speed encapsulation with predefined static header stored in the memory prior sending frames out via L3 interface. Because it is a basic device without any sophisticated features like VLAN and fragmentation support, the “Ethernet Hardware Encapsulator” may become a good academical project covering full hardware design cycle of a communication system and developing an embedded software for it. It demonstrates how to implement both “control” and “data” planes that communicate with each other within a single SoC (system-on-chip) system.

“EHA – Ethernet Hardware Encapsulator” provides a base for further project development – the fully functional verified “store-and-forward” buffer as well as SoC environment that is used as a testbed for “”.

Please watch this video demonstrating working hardware developed during the course of the project:

Documentation and source code for “EHA – Ethernet Hardware Encapsulator” project can be found at:


“ Ver2”:

Another feature is a “fragmentation support” which is being developed in “ – Ver2” project.

For some telecom operators fragmentation support is not required as they own fibre links and their equipment can natively support jumbo frames. In this case transit of original ethernet frame of maximum size of 1500bytes with additional L3 header is not a problem.
On the contrary small ISPs often use internet for overlay transport which imposes strict MTU limitations. So the pseudowire solution they choose must cope with fragmentation issues either via workarounds such as “TCPMSS clamping” or by having fragmentation assembly algorithms implemented in the software which are CPU intensive and slow. “ Ver2” proposes original method of assembling frame’s fragments at line rate speed totally within the datapath with zero CPU/Software involvement.

Please watch the video demonstrating this principle here:

The rest of the documentation proposing architecture of the receiver can be found here: